Download Reliability, Availability and Serviceability of by Érika Cota, Alexandre de Morais Amory, Marcelo Soares PDF

By Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski

ISBN-10: 1461407907

ISBN-13: 9781461407904

ISBN-10: 1461407915

ISBN-13: 9781461407911

This publication offers an outline of the problems on the topic of the try, analysis and fault-tolerance of community on Chip-based structures. it's the first e-book devoted to the standard features of NoC-based structures and should function a useful connection with the issues, demanding situations, suggestions, and trade-offs relating to designing and enforcing state of the art, on-chip conversation architectures.

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2002; Larsson 2005; Silva et al. 2006; Wang et al. 2007) and should be the prime reference on this. The reason for including this section here is to give the reader a brief introduction on the SoC testing field so he/she can follow the rest of this book. 1 Conceptual Test Architecture Zorian et al. (1998) introduced the conceptual test architecture for embedded cores as well as the nomenclature for its elements that has been used in the literature. The conceptual architecture, shown in Fig. 8, is composed of four basic elements: – A test stimuli source for the real-time test pattern generation; – A test sink for the reception and evaluation of the test responses; – A Test Access Mechanism (TAM) for the transportation of the test data from the test source to the core and from the core to the test sink; – A core wrapper, for the connection of the core terminals to the TAM terminals, providing the mechanisms for isolation and integration of the core to the system during test.

1 (1994). The basic assumption of these approaches is that many cores being used at the time were ASICs (application-specific integrated circuits) in the past, and the boundaryscan was already implemented for those modules. Moreover, as the JTAG mechanism requires only five extra pins at system-level, pin count would be low. Some authors used the advantages of the IEEE Std 1149 to deal with hierarchical SoCs (Li et al. 2002a, b). However, the inclusion of a TAP controller into a core makes the integration of such a core into a SoC more difficult (Lousberg 2002), since an extra level of controlling is required for each TAPed module.

3b. 32 Fig. 4 Generic BIST architecture 3 Systems-on-Chip Testing chip Test pattern generator BIST controller Core of the Circuit under test Test response analyzer Test go/no go Scan-based testing can improve accessibility to the internal signals of the chip but the serial nature of the scan chain reduces the maximum possible test frequency and precludes tests that must be applied in the nominal operational frequency of the circuit. To tackle this problem, Built-In Self Test (BIST) strategies can be used.

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Reliability, Availability and Serviceability of Networks-on-Chip by Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski


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