By Stéphane Donnay, Georges Gielen
ISBN-10: 0306481707
ISBN-13: 9780306481703
ISBN-10: 140207381X
ISBN-13: 9781402073816
This booklet is the 1st in a sequence of 3 devoted to complicated subject matters in Mixed-Signal IC layout methodologies. it truly is one of many effects accomplished via the Mixed-Signal layout Cluster, an initiative introduced in 1998 as a part of the TARDIS undertaking, funded by means of the ecu fee in the ESPRIT-IV Framework. This initiative goals to advertise the improvement of recent layout and attempt methodologies for Mixed-Signal ICs, and to speed up their adoption via business clients. As Microelectronics evolves, Mixed-Signal thoughts are gaining an important significance as a result of the extensive unfold of functions the place an analog front-end is required to force a fancy digital-processing subsystem. during this feel, Analog and Mixed-Signal circuits are famous as a bottleneck for the marketplace popularity of Systems-On-Chip, as a result of the inherent problems fascinated about the layout and try out of those circuits. in particular, difficulties bobbing up from using a typical substrate for analog and electronic parts are a major proscribing issue. The Mixed-Signal Cluster has been shaped via a gaggle of eleven study and improvement tasks, plus a selected motion to advertise the dissemination of layout methodologies, recommendations, and helping instruments constructed in the Cluster tasks. the total motion, finishing in July 2002, has been assigned an total finances of greater than eight million EURO.
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Extra resources for Substrate noise coupling in mixed-signal ASICs
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25] S. Mitra, R. A. Rutenbar, L. R. Carley and D. J. Allstot, “A methodology for rapid estimation of substrate-coupled switching noise,” proceedings IEEE Custom Integrated Circuit Conference, pp. 129-132, May 1995. [26] K. Joardar, “A simple approach to modeling crosstalk in integrated circuits,” IEEE Journal of Solid-State Circuits, Vol. 29, no. 10, pp. 1212-1219, October 1994. Chapter 2 SUBSTRATE NOISE GENERATION IN COMPLEX DIGITAL SYSTEMS Analysis and experimental verification Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu IMEC - DESICS, Kapeldreef 75, B-3001 Leuven, Belgium Abstract: More and more system-on-chip designs require the integration of analog circuits on large digital ASICs and will therefore suffer from substrate noise coupling.
When the backside is made conductive and left floating, the behavior is very similar for small distances such as in Figure 1-11 (a). However, as the space between the surface contacts reaches the low-resistivity backside becomes a preferred path for the current. For d close to the wafer thickness — see Figure 1-11 (b) — more than 50% of the total current is flowing through the backside contact. Therefore, the model is improved to separate the lateral component, from the vertical one, Figure 1-11 (c) shows how, when the distance further increases, the lateral effect becomes negligible causing the overall resistance value between the surface contacts to level off.
In chapter 6, we will describe a simulation methodology that makes it possible to accurately and efficiently simulate the substrate noise voltage, and apply it to this 86Kgate digital filterbank ASIC and verify against measurements. In this chapter we will also use some simulation results generated with the methodology described in detail in chapter 6. 1 Measurement results Figure 2-12 shows a comparison of the measured and simulated substrate noise voltage when the digital circuit is operating in 16 times up-conversion mode.
Substrate noise coupling in mixed-signal ASICs by Stéphane Donnay, Georges Gielen
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