By Marcus T. Schmitz
ISBN-10: 0306487365
ISBN-13: 9780306487361
ISBN-10: 1402077505
ISBN-13: 9781402077500
System-Level layout ideas for Energy-Efficient Embedded structures addresses the advance and validation of co-synthesis options that let a good layout of embedded platforms with low power dissipation. The e-book presents an summary of a system-level co-design circulation, illustrating via examples how procedure functionality is stimulated at quite a few steps of the circulation together with allocation, mapping, and scheduling. The publication locations targeted emphasis upon system-level co-synthesis innovations for architectures that comprise voltage scalable processors, that could dynamically alternate off among computational functionality and tool intake. in the course of the e-book, the brought co-synthesis options, which goal either single-mode structures and rising multi-mode purposes, are utilized to various benchmarks and real-life examples together with a pragmatic shrewdpermanent phone.
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Additional resources for System-Level Design Techniques for Energy-Efficient Embedded Systems
Sample text
The power dissipated by these currents is given by: where is the effectively switched load capacitance of the bus lines, is the operational voltage of the bus, and is the operational frequency at which bits are transfered over the bus. Important for the battery-lifetime, however, is the drawn energy: where denotes the number of bus cycles needed by communication One possibility to reduce this energy dissipation is to encode the data before transferring it. Such bus-encoding techniques have been investigated with the aim of reducing the switching activity [22, 114, 141].
4. 4). This can be achieved by generating a mapped-and-scheduled task graph (MSTG) structure, which is a transformed copy of the initial task graph. 5 illustrates this transformation. 5. Capturing the mapping and schedule information into the task graph by using pseudo edges and communication task tionality. Secondly, all nodes mapped to a certain PE or CL are traversed in chronological order of execution and linked by pseudo-edges, if an edge does not already exist. In this way, the schedule and mapping are inherited into the task graph, and the influence of a task extension can be easily propagated through the system schedule by traversing the MSTG in a breadth-first order.
1 motivates the need for a refined voltage selection that accounts for power variations. 2 introduces a new voltage scaling technique which accounts for power variations. 3. 4. 1 SYSTEM-LEVEL DESIGN TECHNIQUES Motivation This section motivates the consideration of power variations during the voltage scaling. The aim of this consideration is to improve the efficiency with which DVS can be applied. , unused circuity is selectively “turned off” by stopping the clock signal to it [45, 146]; this holds also for DVS-PEs [34].
System-Level Design Techniques for Energy-Efficient Embedded Systems by Marcus T. Schmitz
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