By Ken Kundert, Olaf Zinke
ISBN-10: 1402080441
ISBN-13: 9781402080449
ISBN-10: 140208045X
ISBN-13: 9781402080456
The Designer's advisor to Verilog-AMS offers Verilog-AMS, the recent analog and mixed-signal extensions to the commonly used Verilog description language. It starts off by way of describing a rigorous and confirmed top-down layout method. Top-down layout is commonly visible because the key to having the ability to layout very huge and complicated mixed-signal circuits and it really is enabled by way of Verilog-AMS. Verilog-A and Verilog-AMS are then brought with no assuming that the reader has a historical past in behavioral modeling. eventually, it incorporates a entire reference consultant for the language. The Designer's consultant to Verilog-AMS is greatly cross-referenced and listed, making it an amazing reference for either Verilog-A and Verilog-AMS. A significant other site, www.designers-guide.com, presents digital copies of the entire types utilized in this ebook, a library of user-contributed types, a dialogue discussion board, extra files on simulation and modeling, and different precious fabric. The Designer's consultant to Verilog-AMS is written for analog and mixed-signal designers, relatively these designing greater and extra complicated circuits.
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Additional resources for The Designer's Guide to Verilog-AMS (The Designer's Guide Book Series)
Example text
The difference is nodes are not given in the port list in a module definition, and one does not specify the direction of nodes. 5p164). This node defines zero potential for all disciplines, and as such it does not have a discipline itself. Local access to the reference node is provided through the ground statement. ground gnd; The ground statement defines a name, in this case gnd, that is used in the local context to refer to ground. The circuit itself is constructed by creating instances of predefined modules, wiring them together by connecting them to nodes, and specifying parameters for them.
All blocks are simulated at the transistor level in the context of the system (mixed-level simulation) in order to verify their functionality and interfaces. Areas of special concern, such as critical paths, are identified up front in the verification plan and simulated at the transistor level. The performance of the circuit is verified by simulating just the signal path or key pieces of it at the transistor level. Finally, if start-up behavior is a concern, it is also simulated at the transistor level.
In addition, the use of mixed-level simulation dramatically improves the team’s ability to verify complex circuits. 4 Allows Parallel Execution of Design Tasks Reducing time-to-market is an important way in which design teams can increase their chance of success and the returns of their products. Part of the reduction in timeto-market is a result of the improved productivity and effectiveness of the design team, as described above. However, a rigorous top-down design methodology also has the benefit in that it allows more engineers to be effectively engaged in the development process at the same time, resulting in a further decrease in time-to-market.
The Designer's Guide to Verilog-AMS (The Designer's Guide Book Series) by Ken Kundert, Olaf Zinke
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