By Michael Keating Synopsys Fellow
ISBN-10: 1441985859
ISBN-13: 9781441985859
This e-book tackles head-on the demanding situations of electronic layout within the period of billion-transistor SoCs. It discusses primary layout ideas in layout and coding required to supply powerful, functionally right designs. It additionally offers particular concepts for measuring and minimizing complexity in RTL code. eventually, it discusses the tradeoff among RTL and high-level (C-based) layout and the way instruments and languages needs to growth to handle the desires of tomorrow’s SoC designs.
* offers an simply obtainable advisor that allows readers to put in writing greater, extra verifiable code for advanced SoCs;
* Describes recommendations for winning SoC layout, together with simplifying RTL layout, lowering complexity in control-dominated designs, decreasing complexity in info course ruled designs, and simplifying interfaces;
* Discusses the tradeoff among RTL and high-level (C-based) layout and the way instruments and languages may still boost to fill destiny needs.
Early compliment for the easy paintings of SoC Design…
I have loved examining and reviewing the draft fabric for this booklet as Mike has constructed and subtle the content material. His readability and perception, won from operating with various mutual buyers and SOC designers, shines through.
Working in an the place winning IP deployment is prime to product good fortune, i discovered that this ebook addresses virtually what the fashion designer needs to specialize in, from specification, partitioning and fresh interfacing via implementation to verification.
Highly instructed no matter if you're newly beginning out in SoC layout, otherwise you are an veteran weighed down with ever extra complicated process integration challenges.
David Flynn
Fellow, learn & improvement, ARM Ltd
Part-Time vacationing Professor in Electronics and laptop technology, college of Southampton, UK
Read Online or Download The Simple Art of SoC Design: Closing the Gap between RTL and ESL PDF
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Additional resources for The Simple Art of SoC Design: Closing the Gap between RTL and ESL
Example text
In particular, all the code (all the actions described by the code) for a particular state was in one place. Relocating Other Sequential Code Our next step was to examine the rest of the sequential code in the module. Our goal was to move this code from separate sequential processes (always@(posedge clk) blocks in the original code) into the central state machine. We found that there were basically two types of code. One type looks as follows: if ((prev_state_bcu == RDQ1) && (state_bcu == RDQ2)) begin case (fsm_q_sel) TXQ: begin txqreq_rr[fsm_txqnum_sel] <= bcu_rdata[F_RAO_RR]; txqreq_tag[fsm_txqnum_sel]<= bcu_rdata[F_RAO_TAG]; … In this case, it was straightforward to move this code into the state machine, as part of the code for state RDQ2.
As a side effect, during verification and debug, engineers are constantly dealing with code that they did not write, and which they may never have looked at before. They may not be experts on the bus protocols used on the chip or the interface protocols used in the I/O for the chip. Another way to look at this paradigm shift is this: in previous generations of design, chips were designed by teams of engineers. Now they are designed by a network of engineers. Managing this network is much more complex than managing a team.
We partitioned the design into the following files: • • • • • input and output declarations internal declarations of wires, registers and parameters all combinational code (with a few exceptions, explained below) all sequential code (with a few exceptions, explained below) the top level code, consisting of: ○ ○ ○ ○ the module declaration ‘include statements to include the other files combinational code that directly drives primary outputs sequential assignments that simply pipeline primary inputs With this partitioning, virtually all the real action of the module was contained in two files: the combinational code and the sequential code.
The Simple Art of SoC Design: Closing the Gap between RTL and ESL by Michael Keating Synopsys Fellow
by Michael
4.2