Download Verilog for behavioral modeling by Tzartzanis N. PDF

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16'bx : 16'b0; 2'b10: out = in2; 2'b11: out = in3; 2'bx0, 2'bz0: out = flag ? : aluOp = 3'b100; 6'b110110: aluOp = 3'b101; endcase Nestoras Tzartzanis 40 // ?

AluOp = 3'b100; 6'b110110: aluOp = 3'b101; endcase Nestoras Tzartzanis 40 // ?

0) else • else-clause is optional and is always associated with the closest previous if that lacks an else • Example if (index > 0) if (rega > regb) result = rega; else // else applies to preceding if result = regb; Nestoras Tzartzanis 37 February 3, 1998 EE577b  Verilog for Behavioral Modeling Case Statement • Case statement is a special multi-way decision statement: reg [1:0] sel; reg [15:0] in0, in1, in2, in3, out; case (sel) 2'b00: out = in0; 2'b01: out = in1; 2'b10: out = in2; 2'b11: out = in3; default out = 16'bx; endcase • The default statement is optional • If all comparisons fail and the default is not given, none of the case statements is executed Nestoras Tzartzanis 38 February 3, 1998 EE577b  Verilog for Behavioral Modeling Case Statement (cond) • Case statement used to trap x and z values: reg [1:0] sel, flag; reg [15:0] in0, in1, in2, in3, out; case (sel) 2'b00: out = in0; 2'b01: out = in1; 2'b0x, 2'b0z: out = flag ?

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