By Peter A. Beerel
Skip the constraints of synchronous layout and create low strength, better functionality circuits with shorter layout instances utilizing this functional advisor to asynchronous layout. the basics of asynchronous layout are coated, as is a big number of layout kinds, whereas the emphasis all through is on useful options and real-world purposes.
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Additional resources for A Designer's Guide to Asynchronous VLSI
However, creating senders and receivers that react to both phases of the data and control wires often leads to less efficient control circuits, owing to the substantially lower mobility in P-transistors compared with that in N-transistors. Various block implementations for 1-of-N channels will be discussed in Chapters 11 and 12. In addition, block implementations that use a variant known as a 1-of-Nþ1 channel will be discussed in Chapter 11. The 1-of-Nþ1 channel has an additional request signal between sender and receiver to enable higher performance.
Non-linear pipelines Most high-performance architectures are not linear pipelines and thus buffers with multiple input and output channels are often needed. A fork is a buffer with one input channel and multiple output channels. 18. (a) Merge and (b) split non-linear conditional pipeline buffers. input channel to both output channels. A join is a buffer with multiple input channels. Buffers with multiple inputs and outputs are both forks and joins. Buffers are unconditional if they wait for input tokens on all input channels and generate tokens on all output channels.
Thus, the design has capacity or static slack 2. This asynchronous pipelined behavior yields a built-in notion of flow control, which makes system design using a crossbar for module-to-module communication somewhat easier than using synchronous alternatives. With some effort it can also be shown that this implementation is deadlock-free. If the channels can be arbitrarily pipelined to optimize performance while preserving correctness then the design is called slack elastic . Unfortunately, the simple design described above is not slack elastic.
A Designer's Guide to Asynchronous VLSI by Peter A. Beerel