By Valeria Bertacco
ISBN-10: 0387244115
ISBN-13: 9780387244112
ISBN-10: 0387299068
ISBN-13: 9780387299068
Scalable Verification with Symbolic Simulation offers fresh developments in symbolic simulation-based options which noticeably increase scalability. It overviews present verification ideas, either in line with common sense simulation and formal verification tools, and unveils the internal workings of symbolic simulation. The center of this booklet makes a speciality of new suggestions that slender the functionality hole among the complexity of electronic structures and the constrained skill to ensure them. particularly, it covers a variety of recommendations that take advantage of approximation and parametrization tools, together with quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations in accordance with disjoint-support decompositions.
In structuring this publication, the author’s desire used to be to supply attention-grabbing studying for a huge diversity of layout automation readers. the 1st chapters offer an outline of electronic structures layout and, particularly, verification. bankruptcy three studies mainstream symbolic strategies in formal verification, dedicating such a lot of its concentration to symbolic simulation. The fourth bankruptcy covers the mandatory rules of parametric varieties and disjoint-support decompositions. Chapters five and six concentrate on contemporary symbolic simulation innovations, and the ultimate bankruptcy addresses key themes desiring additional research.
Scalable Verification with Symbolic Simulation is for verification engineers and researchers within the layout automation field.
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Extra resources for Scalable Hardware Verification with Symbolic Simulation
Example text
Pseudo-random simulation is mostly used to provide chip-level validation and to complement stand-alone testing validation at the module level. This approach involves running logic simulation with stimulus generated randomly, but within specific constraints. For instance, a constraint could specify that the reset sequence is only initiated 1% of time. Or, it could specify some high-level flow of the randomly generated test, while leaving the specific vectors to be randomly determined [AGL+95, CIJ+95, YSP+99].
For instance, such property could specify that if the system is properly initialized, it never deadlocks. Or, in the case of pipelined microprocessors, one property could be that any issued instruction completes within a finite number of clock cycles. The proof of properties such as these, requires, first of all, to construct a global state-graph representing the combined behavior of all the components of the system. After this, each state of the graph needs to be inspected to check if the property holds for that state.
We use the symbol B to denote the Boolean algebra defined over the set {0,1). A symbolic variable is a variable defined in B. A logic function, or Boolean function, is a mapping F : Bn --t BM. In the attempt to ease the reading of the theoretical presentations in this book, we use lower-case letters to denote symbolic variables, and upper-case to denote functions. In addition, scalar functions, F (xl, . ,xn) : Bn --t B are represented by regular face literals, while vector-valued functions are represented in boldface.
Scalable Hardware Verification with Symbolic Simulation by Valeria Bertacco
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